Verilog Adventures

In the past week I have had some free time to do some experimentation. I may as well do some reflection on what I did

Verilog

In short as I am interested in getting into digital electronics, computer architecture and FPGAs, I decided to learn some verilog

  1. https://www.chipverify.com/verilog/verilog-simulation
  2. An Introduction to Verilog: https://www.youtube.com/watch?v=q1QwC3YlHG0
  3. Verilog on EDA Playground Starting Tutorial: https://www.youtube.com/watch?v=odjQVpN4aF0

Tools Used

  1. EDA Playground: https://www.edaplayground.com/
  2. Icarus Verilog: Just use your package manager to install and follow this https://iverilog.fandom.com/wiki/Getting_Started

Basic concepts

I have made some reference code in here. The main concepts I remembered are

  1. Verilog is a Hardware Description Language

    • You describe how a digital electronic logic component (a module) functions/ what the schematic is
    • You describe a testbench, which connects to the module, runs tests and displays values

  2. Behavioural Modelling vs Gate Level Modelling

    • Behavioural Modelling : Similar to normal programming, describing how a module functions
    • Gate Level Modelling : Describing wires and how gates connect to one another

  3. Data Types

    • Basic Data Types

      • Wires: To connect Electrical components
      • Registers: Controllable bits (0, 1, x(unknown state), z(high impedence))
      • Integers, Real and Time (To store simulation time values)

    • Arrays and Vectors

      • Arrays: Just like arrays in normal programming languages
      • Vectors: A groups of bits (like how 8 bits = 1 byte). You can modify the entire vector at once unlike an array
      reg [7:0] reg_vector;    
reg_vector = 11;          // Integer
reg_vector = 8'b10001010; // Binary
reg_vector = 8'h41;       // Hexdata
reg_vector [7:4] = 4'h5;  // Slicing
reg_vector[0] = 0;

  4. Control Structures

    • Building blocks
      • initial begin {statements} end
      • `always @ event begin {statements end}``
      • posedge _ or negedge _: runs only when the value becomes positive or negative
    • Behavioural Modelling
      • if-else, case statements
      • Loops: For loops, while loops

  5. Input Output

    • $display to output something to the screen. Can format with variable values.

I may want to revisit this topic to provide a more comprehensive tutorial on verilog, but for now, I'm satisfied with this. I'll probably use it to experiment with my FPGA and stuff

Personal Website Updates

I have made a better CTF Writeup generator, which converts the CTF writeups in my github repository Programming Crappy Solutions into proper webpages. The idea is to make them more accessible from my website, since I'm churning out many writeups. In short I:

  1. Used a python program to better tag and extract the writeups from my repository
  2. Converted them from a Markdown site to HTML webpage
  3. Put proper formatting, similar to the one on the Github page

I am planning to add more functionality such as

  1. Maybe add tagging on the related concepts?
  2. Clean up my repository such that some writeups (for instance, challenges with half done/ incomplete writeups) do not show up
  3. Make a better search system (Similar to the current blog search system)
  4. Link the challenges with the CTF

Others

  1. I'm planning to experiment with Blender Motion Graphics. However, I have no idea what free resources to start with, so maybe I'll look at After Effects Motion Graphics tutorials and then use them in blender

That's it from me today, see you next post!