Starts from 0900

AY23/24 Semester 2

Major Mods

CG2111A

I personally did not like how this module was conducted. It felt like a mismash of various concepts with no coherent flow, and I would have preferred taking a module like EE2028 instead which is more consistent. As this module touches a bit of everything, we didn't really get to deep dive and master the specific concepts. Furthermore, in our semester, the robot run was revamped and things kept changing, so it was rough to plan ahead. I also didn't find the teaching team answers very satisfying to some of my question, like why we cannot connect UART Buses together for example ("its not supposed to work, you just cant" like why?).

And yet, I cannot deny how useful the content this module was, especially since I had to do projects involving some of the concepts here. When I worked with other microcontrollers such as the STM32, I can see how the concepts are applied, and that helped me in writing embedded code and ideating various ideas.

The labs are relatively doable, being done in a pair. To be honest, on my first lab, I did it all on my own before my pair and I realised it was pair work... Nevertheless, prep work is good to have (as with most EPP modules), and there were some labs which I made careless mistakes on.

The theory is relatively doable, though it can be quite challenging. I personally got 15/16 for both quizzes. However, the median would be 11/16 or so.

I screwed up my robot run, couldn't find a parking lot + made several mistakes. It is a 4 person project, but being on the RPi, it is hard to evenly distribute the work and share the robot.

Expected Grade: B+/A-
Actual Grade: A-

EE2026

AY23/24 Semester 2
Lecturer: Prof Chua Ding Juan
Tutorial: Prof
Lab: Christopher Moy

overly summarised review

1. Prof Chua is an amazing lecturer. She was able to break down the concepts well, clarify doubts, engage students with exercises during the lecture + kahoot quizzes. She is one of the best lecturers in the whole of NUS, and I highly recommend going for them.
2. Tutorials are a bit more hit/ miss. The exercises are good practice for the quizzes
3. Labs can be completed at home. They do take some time
4. Verilog Evaluation is quite straightforward. They said you only have 1h to code verilog, but you also have an additional 20min to read the question + plan (on paper). You also have an additional submission attempt to clarify any doubts (which saved my eval)
5. Basic Project is 4 people, you can form your own groups. tbh not too hard, you are given week 7-9 to work on it which is more than enough time. Use the time to think about the open ended project.
6. Open Ended Project is in the same group. For my group we started planning very early, like Week 6, and even so it was very, VERY painful to integrate. I spent 2 whole weeks rallying my team to work on the project and integrating. Regardless, we fit in whatever features we wanted to fit in (we had a relatively ambitious project), and it was quite worth it

• A very important thing is that the project HAS AN INDIVIDUAL COMPONENT, each person is attributed to a specific feature. So in this case there is some incentive for everyone to do a specific part. That said, adjusting expectations of who does what is an issue, so do get that out of the way
• a lot of people in my batch did UART and 2 board comms. My group did 4 boards, 1 master 3 slave
• You have 3 weeks from this, around Week 8 - 11, but when you get your OLED from Week 7, just start planning and working on it, more time to work on the project = more time to fix things for integration

I think there's a trend to hype up this module as hard, but besides the open ended design project (which according to the profs, is only meant to differentiate A and A+), the rest of the content is relatively doable, provided you take the time to understand the concepts. The profs are wary against project inflation (people keep coming up with crazier projects like raytracing).

Also, do put enough attention into your quizzes/ lab assignments because those make up the bulk of your grade

Assessments

1. Midterm Quiz, Final Quiz - 20%, 15%
2. Lecture Quizzes - free 5%
3. Post Lab Graded Assignments - 3%, 6%, 10%
4. Verilog Evaluation - 11%
5. Project - Basic Mods - Standard among all teams - 4% indiv, 7% group
6. Design Project - Come up with whatever you want - 6% indiv, 6% group, integration, 5% presentation + Q&A

Expected Grade: A/A+
Actual Grade: A+

CS2040C

This was one of my more chill modules this semester.

Lectures were decent. Labs were not really involving programming, but more of the problem solving approach. So this involves in class discussion and puzzle solving. Labs are not compulsory, but the exercises (and compulsory VisuAlgo Quizzes) are the kinds of questions which come out for the quizzes and finals, so they are useful.

There are 5 assignments, each involving implementing a data structure or a feature. Since it is mostly implementation, it felt relatively doable to me, though I did get stuck on it sometimes.

The PE is actually relatively doable, but doing a C++ PE + choking during the PE makes it hard to get a good score.

The Quizzes and Finals are relatively straightforward, make sure you can score for it. It involves mostly tracing questions + some explanation questions + MCQs.

Expected Grade: A/A+
Actual Grade: A (prof said 80% for A+ but I guess I choked finals..., still got a top students award though)

MA1508E

I liked the format. It involved a fair bit of MATLAB, and we didn't have to do all the menial tasks as much (like converting to RREF). In return, we were given a lot of conceptual questions which were more challenging, and potentially more useful. This is not to mention MATLAB, which Engineers would need to eventually use.

In this module, we were also given access to all the content right from the start, in a blended learning approach. Weekly realizeit quizzes helped me reinforce my concepts, and I personally used the given lecture notes to absorb the knowledge fast. This DRASTICALLY helped me in my semester as I could finish the content early, leaving more time in the later half of my semester for projects.

However, due to the hectic nature of the sem, I felt that I couldn't appreciate the content as much as I would have liked to.

Expected Grade: A-/A
Actual Grade: A

DTK1234

eh, be consistent in your ILAs (don't have to stress too much about it but do put in effort), chiong for your Design Thinking Journal, and you'll do decent.

Expected Grade: A-/A
Actual Grade: A

PF1101

Expected Grade: B+
Actual Grade: A- (pleasant surprise)

CDE2501

Expected Grade: A-
Actual Grade: B+ (meh)

NGN2001C

I didn't like the vibes of the class, its mainly the prof asking "what do you think", and awkward silences of everyone else waiting around for someone to answer. The pressure to answer and to think of something innovative is something I didn't really like, and it shows to me how NUSC classes can be done in a non-ideal manner.

It didn't help that I didn't like literature either, and I didn't really like the format. I liked some of the readings, but they didn't really vibe with me as much (except for maybe Charlie Chan)

I also wasn't that good at writing essays, so I mostly got Bs for my essays, and 1 B+ 1 A-.

Expected Grade: B
Actual Grade: B+ (I call this a win)